Intel's leadership walks through how advanced process nodes are brought to volume, from yield learning and the lessons of 10nm to the shift from planar transistors to gate-all-around, High-NA EUV, backside power, and CFET. The discussion widens to the chip-to-chip bottleneck that hybrid bonding targets, the supply limits on EUV tooling as AI compute demand grows, and the economics that make foundry scale decisive.
Pat Gelsinger joins a16z's Raghu Raghuram and Guido Appenzeller to discuss how AI is reshaping chip design, why design speed alone will not fix semiconductor bottlenecks, and why power and energy capacity may ultimately limit AI growth. The conversation covers HBM and memory innovation, stacking limits, the shift from copper to optics, consolidation among AI chip startups, and what a VMware for AI agents might look like.
Intel CEO Lip Bu Tan shares his strategic vision for turning around the tech giant, focusing on cultural transformation, strengthening the balance sheet with key investments (including the US government and Nvidia), and driving innovation in foundry, advanced packaging, and new materials. He discusses collaborations like Terafab with Elon Musk, the profound impact of AI on the semiconductor supply chain, and his investment philosophy for the evolving industry, aiming to position Intel for agentic and physical AI at the edge and client, not just centralized compute.