A walkthrough of the memory wall, explaining why raw chip compute growth has not translated into proportional AI workload speedups. It covers arithmetic intensity, the roofline model and ridge points for the B200 GPU, why LLM decode is memory-bound while prefill is compute-bound, and how batching and continuous batching shift workloads toward higher efficiency.
Pat Gelsinger joins a16z's Raghu Raghuram and Guido Appenzeller to discuss how AI is reshaping chip design, why design speed alone will not fix semiconductor bottlenecks, and why power and energy capacity may ultimately limit AI growth. The conversation covers HBM and memory innovation, stacking limits, the shift from copper to optics, consolidation among AI chip startups, and what a VMware for AI agents might look like.
Co-founders of Ricursive Intelligence, Anna Goldie and Azalia Mirhoseini, outline their thesis that AI should design the chips that train AI. They detail their three-phase plan to first accelerate chip design with AI tools 100,000x faster than current software, then become a 'design-less' platform for custom silicon, and finally achieve vertical integration by building their own chips and models.