Hardware acceleration

Hardware Realization and Implementation Security Evaluation of HQC, A NIST PQC Standard

Hardware Realization and Implementation Security Evaluation of HQC, A NIST PQC Standard

This talk by Sanjay Deshpande from Northwestern University explores the critical transition to Post-Quantum Cryptography (PQC) in response to the threat quantum computers pose to current public-key algorithms. It provides a deep dive into the Hamming Quasi-Cyclic (HQC) algorithm, a code-based candidate for NIST standardization. The session focuses on the challenges and innovations in creating efficient and secure hardware implementations of HQC, covering performance optimization for polynomial multiplication and countermeasures against side-channel attacks.

Efficient Homomorphic Integer Computer from CKKS

Efficient Homomorphic Integer Computer from CKKS

A deep dive into the hardware design and implementation of HQC, a post-quantum cryptography scheme. The talk covers performance and security bottlenecks, detailing novel solutions for efficient polynomial multiplication by leveraging sparsity and constant-time methods for generating fixed-weight vectors to thwart side-channel attacks.